June 4, 2010
Murata Manufacturing Co., Ltd.
President/ Statutory Representative Director: Tsuneo Murata
Murata Manufacturing Co., Ltd., in collaboration with Mathematec Corporation, has developed an arithmetic processing IP core for MP3 decoders that uses less than 10% of the power required for conventional general software processing.
With the proliferation of mobile devices with audio music playback features, and other increasingly advanced functions, the challenge is to find ways of reducing power consumption in future designs.
Using Murata's original hardware processing, we have developed an arithmetic processing IP core that will significantly reduce the arithmetic processing load within MP3 decoders. *1
By optimizing circuits with original Murata architecture, used in conjunction with the Spinor® circuit compression technology developed by Mathematec Corporation, we have succeeded in achieving a circuit size and power consumption level that rank among the smallest and lowest ever to have been developed. *2
This product will be made available to customers as a synthesizable soft macrocell. In addition to providing hard macrocells optimized for specific processes, we can also address customer unique requirements.
Compliant with MP3 (ISO/IEC11172-3, ISO/IEC13818-3) standards
| Clock rate: | less than 20 MHz (real time decoding possible at 6 MHz) |
|---|---|
| Circuit size: | logic circuit – approximately 32000 gates, 76 kbit RAM |
| Power consumption: | 0.35 mW (44.1 kHz 128 kbps Stereo, when implemented in IBM9SFLP process) |
Product available starting July, 2010
| *1: | As a rule software or hardware-based implementation of initial MP3 processes (header decoding, Huffman decoding) will be carried out by the customer. Murata's engineering staff will provide technical assistance with these processes upon customer request. |
|---|---|
| *2: | As shown by evaluation results of implementation in the IBM9SFLP process. |
| *3: | Based on company research and observed results, we assume the power consumption of conventional software processing to be approximately 4 mW. |
| Company Name: | Mathematec Corporation |
|---|---|
| Office Location: | Daisan Shomei Building 8F, 1-18-14 Nihonbashi, Chuo-ku, Tokyo 103-0027, Japan |
| Established: | April 13, 2000 |
| Capital: | 214,925,000 yen |
| Description of Business: | The Mathematec Corporation carries out research and development in circuit reduction technology for system LSI and FPGA, as well as the commercialization of this business area. The company integrates mathematical science and technology to design basic electronic circuits which dramatically improve performance and cost efficiency. |
Spinor® is a registered trademark of the Mathematec Corporation
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