Q. Please explain the role of each component of the oscillation circuit.
Q. Which type of capacitor should be used as a loading capacitor in an oscillation circuit?
Q. Please explain possible causes of abnormal oscillation, and appropriate countermeasures.
Q. Please explain possible causes of oscillation stop, and appropriate countermeasures.
Q. Please explain noise-suppressing measures.
Q. What is "spurious oscillation"?
Q. Please explain abnormal oscillations other than spurious oscillation, and their check method.
Each circuit value has the following role:
The feedback resistor determines the bias of the oscillation circuit. Generally, C-MOS IC uses 100k ohms to 10M ohms (normally, 1M ohms) feedback resistance, while TTL IC uses 1k ohms to 10k ohms (normally, 4.7k ohms) feedback resistance because of low I/O impedance. If the feedback resistance is too large, the amount of feedback will be reduced, making the operating point unstable. If the feedback resistance is too small, the gain will be reduced, or the current will be increased (Recently, most ICs intgrates the feedback resistor).
Damping resistor and loading capacitors work as low-passfilter that can suppress abnormal harmonic oscillation by reducing the gain in the high frequency range. Also, the IC gain can be limited and "CERALOCK®" properly match IC, unwanted ringing, overshoot and undershoot can be suppressed. In the kHz band, the damping resistance should be several kilo-ohms, and in the MHz band, it should be between tens ohms and hundreds ohms. The damping resistor is optional.
This parameter is the most important for determining the stability of the oscillation circuit. If the load capacitance is too small, the oscillating waveform will be distorted, resulting in unstable oscillation. If it is too large, oscillation may stop. When compared with the same IC, the oscillation circuit providing lower frequency needs larger capacitance.
When the IC gain is too high, or when TTL or triple-stage buffered IC is used, the bias resistor can be used to change the bias point intentionally in order to reduce the IC gain or suppress unstable oscillation. C-MOS IC uses a bias resistor of 1M ohms to 10M ohms, while TTL uses a bias resistor of several kilo-ohms to 10 kilo-ohms.
Each constant varies depending on the IC and the "CERALOCK®" being used. For details, contact Murata.
A ceramic capacitor with excellent frequency characteristics is most suitable as a loading capacitor in an oscillation circuit, because normally the load capacitance of approx. 3pF to 2200pF is required for an oscillation circuit.
Since the oscillation frequency of the "CERALOCK®" varies depending on the value of the load capacitance, we recommend you select higher-precision type, temperature drift-compensating type (with high Q), and temperature coefficient "0" type (tolerance "J," temperature characteristics "CH"). Generally, you will have no problem using a capacitor providing total tolerance of +/-20% (including the initial capacitance tolerance and fluctuations due to temperature change from -20°C to 80°C). However, you must remember that abnormal oscillation or oscillation stop may occur depending on the IC being used, although this is a rare case.
Judging from Murata's evaluation results, if stable oscillation is provided after the load capacitance is increased/reduced by two steps from the recommended constant under the E6 system, it raises no problem.
Furthermore, you must confirm that the set can operate normally while the load capacitance changes, because the oscillation frequency varies with the change in load capacitance.
In order to distinguish 1 from 2 above, replace the "CERALOCK®" with a capacitor (Cx) with the same capacitance as the "CERALOCK®". In case of Type 2, the circuit can provide normal oscillation even if the "CERALOCK®" is replaced by Cx.
After finding the cause of abnormal oscillation, you must take appropriate countermeasures:
The "CERALOCK®" will develop many kinds of parasitic oscillations (spurious oscillations) in addition to the oscillation with the target frequency (main oscillation frequency). If the oscillation circuit is operated with improper circuit constants, parasitic oscillations may occur. Commonly observed spurious modes are listed in Table 1.
Table 1 Examples of spurious oscillation frequencies by series
| "CERALOCK®" Series (Main frequency) | Abnormal oscillation frequency/mode |
|---|---|
| (1) CSBFB_J Series (430-1250kHz) | 4.5-7MHz/Perpendicular spurious |
| (2) CSTCC/CSTCR/CSTCE-G Series (2.0-12.50MHz) | Triple of rated frequency/Triple wave |
| (3a) CSTCW/CSACW_X Series (20-70MHz) | One third of rated frequency/Fundamental wave |
| (3b) CSTCW/CSACW_X Series (20-70MHz) | Five thirds of rated frequency/Quintuple wave |
Among the "CERALOCK®" Series listed in the above table, (1), (2) and (3b) will develop oscillations at a higher frequency than the main frequency. To lower the gain in high frequency range, you can take the following measures:
a.Increase "CL" (CL1=CL2) (approx. two steps under the E6 system).
b.Add "Rd" (damping resistor: 100 to 10k ohms).
If you use a), the oscillation frequency will slightly decrease, and you need to consider the influence on the sets.
If "CL" and "Rd" are increased too much in case of both a) and b), oscillation will stop.
In case of (3a), the "CERALOCK®" will develop oscillations at a lower frequency than the main frequency. Therefore, you must increase the gain in the high frequency range, or lower the gain in the low frequency range by taking the following measures:
c.Lower "CL" (CL1=CL2) (approx. three steps under the E6 system).
d.Add "Rp" (approx. 1 to 100k ohms), or lower "Rf."
If "CL" is reduced too much in case of c), oscillation becomes unstable. If "Rf" is reduced too much in case of d), oscillation will stop.
The following example shows an abnormal oscillation in a circuit where the "CERALOCK®" serves as a capacitor. We have not established a fixed countermeasure against this type of abnormal oscillation, because an effective method varies depending on the IC being used. However, the following countermeasures can be considered:
e.Change "CL."
f.Make "CL1" and "CL2" unbalanced.
g.Add "Rd."
h.Add "Rb."
If oscillation stop occurs, or oscillation is disabled, you must examine the cause of the problem, such as malfunction of the "CERALOCK®", mismatching between "CERALOCK®" and IC or reset program error. However, if the IC is not operating as an amplifier, oscillation is disabled by any means. Therefore, you must perform IC operation check first. The IC operation can be checked simply by connecting the IC's input terminal to a power supply or ground to confirm whether the output signal is inverted. If the IC serves as an inverter, the output signal must be inverted.
When oscillation is disabled even if the IC serves as an inverter, the "CERALOCK®" (oscillation circuit) must have a problem. Improper circuit constants, or malfunction of the "CERALOCK®" can be considered as the cause of this problem. If the circuit constants are proper, the circuit will develop normal oscillation even if the "CERALOCK®" electrical characteristics become unstable within the ratings (for example, the resonance resistance (R1) may be slightly increased). If the circuit constants are not proper, oscillation may stop due to the fluctuations in "CERALOCK®" electrical characteristics.
The oscillation stability relative to fluctuations in "CERALOCK®" electrical characteristics in an oscillation circuit can be referred to as oscillation excess gain. The oscillation excess gain is correlated with "R1" of the "CERALOCK®": When "R1" is increased, the oscillation excess gain will be reduced. To check the oscillation stability, measure the characteristics of a single "CERALOCK®" by using an impedance analyzer or network analyzer. In comparison between a defective "CERALOCK®" and a normal one, you can see some difference in their characteristics. If oscillation stop occurs during a temperature change, check their characteristics by changing the operating temperature with a dryer or freezer.
If oscillation stop occurs with the normal "CERALOCK®", or at a high probability, the circuit constants may be improper. In this case, you must check the circuit constants, because circuit constants may significantly vary depending on the IC being used. Among the circuit constants, load capacitance "CL" (CL1/CL2) is the most important parameter. If "CL" is too high, the circuit gain will be reduced: If "CL" is too small, the circuit cannot provide proper phase difference, which also causes oscillation excess gain to be reduced. To check this parameter, measure the amplitude characteristic of load capacitance. For this purpose, change "CL" (CL1=CL2) from the standard value (e.g. capacitance of 3-terminal product) in the range of 1/10 to 10 times, and observe the change in input (V1) amplitude. When the proper load capacitance is provided, the largest amplitude must be observed.
On the other hand, if feedback resistance (Rf) is too large, feedback is disabled when the PCB's insulation resistance is reduced due to any cause, resulting in oscillation stop. This problem is caused by unstable DC bias. To examine the cause of this problem, measure the bias voltage with a probe connected to the IC's output terminal after removing the "CERALOCK®", and you will find that the bias voltage is nearly equal to VDD, although it must be VDD/2 in normal conditions.
You can solve this problem by adding an external feedback resistor of approx. 1M ohms to the oscillation circuit.
The "CERALOCK®" provides lower Q than quartz resonators, and large capacitance between terminals. Therefore, the noise (unwanted radiation noise) affecting the "CERALOCK®" is lower than that for quartz resonators. If you still have a problem with noise on the "CERALOCK®", you can suppress the noise to some extent by changing the constants of the oscillation circuit. For this purpose, the following three methods are commonly used:
If the load capacitance is increased, the effect of the low-pass filter will be enhanced, causing the microwave noise to be reduced. In this case, however, the oscillation frequency will be slightly reduced. If the load capacitance is increased too much, oscillation will stop.
Adding a damping resistor further enhances the load capacitance and the effect of the low-pass filter, and also corrects the matching between the "CERALOCK®" and the IC being used, enabling the reflective ringing to be suppressed. Also, this can reduce current consumption, resulting in noise suppression. If the damping resistance is increased too much, oscillation will stop.
Inserting ferrite beads lowers the microwave gain, resulting in noise suppression. If the inductance or loss from the ferrite beads is too large, oscillation stop or abnormal oscillation may occur.
Even if you use any of the above methods 1) to 3), it may not be effective in noise suppression, depending on the IC and "CERALOCK®" being used. Particularly, with the "CERALOCK®" using 3rd-overtone oscillation, the circuit constants provide little oscillation excess gain, and you must thoroughly consider the circuit constants.
For the inverter of the oscillation circuit using the "CERALOCK®", we recommend you select the unbuffered type (4069UB/74HCU04) comprised of the C-MOS single-stage inverter. Although oscillation is enabled with the triple buffered type (4049/4011/74HC04) comprised of triple-stage inverters, or with the Schmitt trigger type, we cannot recommend these types, because they may frequently develop abnormal oscillation. That is because the triple buffered type and the Schmitt trigger type provide extremely high gain, so that the oscillation attributed to "CR" of the circuit or "LC" of the wiring, or the ring oscillation (caused by gate delay time) will be superimposed on the waveform of the "CERALOCK®". The CR/LC/ring oscillation can be reduced to some extent by providing proper circuit constants, but it is impossible to eliminate these oscillations completely.
The oscillation circuit is the heart of the sets, because it determines the clock frequency. We cannot recommend using a NAND or NOR gate IC, because it is designed as a triple buffered type, and therefore it may frequently develop abnormal oscillation when used in an oscillation circuit. To control oscillation ON/OFF status, controlling the output from the oscillation circuit is a preferable method, rather than inserting a gate IC in the oscillation circuit. For this purpose, you must prepare a dedicated oscillation circuit after thorough consideration, instead of building an oscillation circuit using a surplus gate IC, or inserting an ON/OFF control device in the oscillation circuit.
Recently, ICs incorporating only two unbuffered gates are also available for an oscillation circuit.
Circuit that may frequently develop abnormal oscillation
Triple buffered IC
With ON/OFF control device in oscillation loop
Circuit that provides stable oscillation
Unbuffered IC
Without ON/OFF control device in oscillation loop
As the temperature of piezoelectrics is raised, the tetragonal crystalline structure will change to a cubic crystalline structure at a certain temperature (transformation point). This temperature is referred to as "Curie point" or "Curie temperature." When the tetragonal crystalline structure is changed to the cubic crystalline structure, the material will lose piezoelectricity. Therefore, once a piezoelectric material is exposed to a temperature higher than the Curie point, it does not recover piezoelectricity even if it is restored to room temperature (This state is called "dipole"). To recover the piezoelectricity, the material must be polarized with application of a high DC voltage.
In principle, the "CERALOCK®" can be classified into two series: kHz-band type and MHz-band type. The product categories are identified by the vibration mode. However, any type of "CERALOCK®" provides oscillation frequencies (parasitic oscillation) different from the main oscillation frequency. The oscillation with parasitic frequency is called spurious oscillation. You can check the behavior of the parasitic oscillation by using an impedance analyzer such as HP4294 (manufactured by Agilent Technologies).
Generally, any type of resonator provides odd-multiple overtone frequencies. However, the "CERALOCK®" will rarely develop spurious oscillation due to overtone frequency, except for the resonators that inherently use the 3rd-overtone frequency, such as the CSTCW/CSACW_X Series.
You can check the spurious oscillation due to overtone frequency by measuring the oscillation frequency. If the oscillation frequency is nearly triple the target frequency, it is regarded as spurious oscillation due to 3rd-overtone frequency.
When the CSTCW/CSACW_X Series is used, spurious oscillation with a fundamental wave (1/3 frequency) or quintuple wave (5/3 frequency) can be observed, because 3rd-overtone oscillation frequency is equal to its target oscillation frequency.
Oscillation circuit may develop abnormal oscillation by itself, depending on the circuit type. To differentiate the abnormal oscillation attributed to the oscillation circuit from the spurious oscillation of the "CERALOCK®", you must take a reading of a frequency counter to check if the reading is equal to the frequency of the spurious oscillation mode, or change the power supply voltage to check if there is a large change in frequency (+/-1% or more).
The following table lists examples of frequently observed abnormal oscillations.
| Type of oscillation | Cause |
|---|---|
| CR oscillation | When the IC gain is high, CR oscillation occurs depending on the electrostatic capacitance (Cf) and load capacitance (CL) of the "CERALOCK®", and the internal resistance (R) of the IC. The frequency varies with a change in power supply voltage. |
| LC oscillation | When the IC gain is high, LC oscillation occurs depending on the conductance (C) and inductance (L) of the wiring (Mostly, the oscillation frequency is 10MHz or higher). The frequency varies with a change in wiring. |
| Ring oscillation | Ring oscillation is caused by delay of the time constant used in the multistage inverter-type IC (Mostly, the oscillation frequency is 10MHz or higher). |
You can check if the circuit develops abnormal oscillation by using the following methods:
A.Change the power supply voltage or circuit constants during measurement at oscillation start.
If abnormal oscillation occurs, the waveform immediately after oscillation start becomes unstable.
B.Turn on/off the power supply.
When the power supply is turned on, abnormal oscillation occurs.
C.Raise the power supply voltage gradually
from 0V.
This method is effective for resonators using 3rd-overtone frequency such as the CSTCW/CSACW_X Series. When the power supply voltage is low, oscillation starts with the fundamental wave. However, the fundamental wave may be retained after the power supply voltage reaches the target voltage.
D.Raise or lower the operating temperature by using a dryer or freezer.
While the circuit is cooled or warmed, it may easily develop abnormal oscillation.
