The "Reticle Limit" is no longer the finish line—it’s the starting block. As AI models grow exponentially, the traditional monolithic ASIC is hitting a wall. To deliver the next generation of AI CPUs and Accelerators, the industry is shifting its focus from the transistor to the package. The "Core" of modern computing is no longer a single slab of silicon, but a complex, heterogeneous ecosystem of chiplets.

Join us for the third installment of our "Transformation from Chip to Core" series, where we dive deep into the physical and electrical foundations of AI scaling. We will explore how advanced packaging and innovative power delivery are solving the "Memory Wall" and "Power Wall" challenges.

What we will cover:
- The Move to Chiplets: Why disaggregation is the only path forward for high-yield, high-performance AI ASICs.

- Advanced Packaging Frontiers: A technical look at 2.5D/3D integration, CoWoS, and the role of high-bandwidth interconnects.(IC generation change from mono to 2.5D + 3D)

- Solving the PDN Challenge: Strategies for managing high current densities and minimizing IR drop in dense AI clusters.

- Heterogeneous Integration: How to balance thermal management with signal integrity when mixing nodes and chiplet.

Presenters: